1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a capacitor incorporated in a semiconductor device and a method for forming the same.
2. Description of Related Art
At present, as can be seen in a DRAM (dynamic random access memory), a high integration density is demanded in semiconductor devices. In order to fulfil this demand, an area required fro each memory cell in the DRAM has been extremely reduced. For example, in a 1 MDRAM or 4 MDRAM, a 0.8 .mu.m rule has been adopted in the semiconductor device design, and further, in a 16 MDRAM, a 0.6 .mu.m rule has been adopted.
As mentioned above, the integration density is increased more and more, namely, a memory capacity is increased more and more in a semiconductor memory. However, in order to elevate the production efficiency and to lower a production cost, it is not allowed to increase the size of a semiconductor device chip. Because of this, how small a memory cell is formed, is an important problem to be solved in the semiconductor device.
However, if the area of the memory cell is reduced, the amount of electric charges stored in the memory cell correspondingly become small.
Therefore, it has become difficult to realize a high integration density of memory cells and at the same time to ensure a necessary amount of electric charge stored in each memory cell.
Under the above mentioned circumstance, a memory cell having a trench capacitor and a memory cell having a stacked capacitor have been proposed and reduced in practice.
As compared with the memory cell having the trench capacitor, the memory cell having the stacked capacitor has an excellent soft-error resistance and an advantage in which no damage is given to a silicon substrate. Therefore, the stacked capacitor type memory cell is expected as a next generation memory cell structure.
As the stacked capacitor, there is proposed a stacked capacitor formed by utilizing a HSG (hemi-spherical (silicon crystalline) grain) technique (See for example Japanese Patent Application Pre-examination Publication No. JP-A-5-110023, an English abstract of which is available from the Japanese Patent Office and is incorporated by reference in its entirety into this application). The stacked capacitor proposed by JP-A-5-110023 is constituted of a capacitor lower plate, a capacitor insulator film and a capacitor upper plate, the capacitor lower plate being electrically connected through a contact hole formed in an interlayer insulator film, to a MOSFET (metal-oxide-semiconductor field effect transistor) formed in a semiconductor substrate.
Here, the HSG technique is to form a number of hemi-spherical grains on a surface of a storage electrode (capacitor lower plate), so that a surface area of the storage electrode is substantially increased, with the result that an increased capacitance is realized.
In order to form the storage electrode having the surface covered with the hemi-spherical grains mentioned above, various processes were proposed. For example, JP-A-5-110023 proposes to deposit a voidless polysilicon film or an amorphous silicon film by a LPCVD (low pressure chemical vapor deposition) process as an underlying film of a capacitor lower plate, then to form a natural oxide film on the underlying film, and to deposit another amorphous silicon film on the natural oxide film by a LPCVD process, as an overlying film of the capacitor lower plate, and further to conduct a heat treatment to the overlying amorphous silicon film, so that a surface-roughed polysilicon film having a concavo-convex upper surface is formed.
In this process, when the overlying amorphous silicon film is heat-treated, migration occurs in the amorphous silicon film, so that crystalline grains are formed, with the result that the surface-roughed polysilicon film having the concavo-convex upper surface is formed. In addition, in this process, since crystallinity of the underlying silicon film is prevented from giving any influence to the overlying roughed polysilicon film by the natural oxide film, it is possible to sufficiently roughen the overlying silicon film surface.
Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-7-014797 (which was a publication of Japanese Patent Application No. 140710/1994 filed claiming Convention Priority based on U.S. patent application Ser. No. 08/071904 filed on Jun. 3, 1993, a disclosure of which is incorporated by reference in its entirety into this application), proposes another method for forming a polysilicon layer having a concavo-convex surface. In this method, in order to prevent generation of a dopant defective region occurring when there is used a high temperature dopant migration method for causing, by means of a heat treatment, the dopant to move upward from a layer underlying under a surface-roughened polysilicon layer, a silicon dioxide layer is formed on a polysilicon layer, and a silicon layer is formed on the silicon dioxide layer while being exposed to a dopant gas, with the result that a polysilicon layer having a concavo-convex surface is formed.
Both of JP-A-5-110023 and JP-A-7-014797 as mentioned above are characterized by enlarging the concaves and convexes formed on a top surface of a capacitor lower plate, but pay no attention to formation of concaves and convexes on a side surface of the capacitor lower plate. Because, in order to increase the capacitance of the memory cell capacitor, it is necessary to form the concaves and convexes not only on the top surface of the capacitor lower plate but also on the side surface of the capacitor lower plate which is exposed when the capacitor lower plate is patterned and which is therefore covered with a capacitor upper plate. Therefore, when the methods of JP-A-5-110023 and JP-A-7-014797 are applied for forming a capacitor on an actual MOSFET, a sufficient capacitance cannot be obtained.
Furthermore, neither JP-A-5-110023 nor JP-A-7-014797 discusses a phenomenon occurring at a boundary between an interlayer insulator film and a capacitor lower plate when the capacitor is connected to a MOSFET formed in the semiconductor device.
Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-5-304273 (which corresponds to U.S. Pat. No. 5,385,863, a disclosure of which is incorporated by reference in its entirety into this application), suggests to form the concaves and convexes on a side surface of a capacitor lower plate by utilizing the HSG technique called a "crystal nucleation". In this crystal nucleation, silicon atoms in the top surface and the side surface of an amorphous silicon film are caused to migrate, with the result that the concaves and convexes are formed on the top surface and the side surface.
However, when the capacitor lower plate is formed in accordance with this crystal nucleation, crystallization of the film starts from a boundary between the capacitor lower plate film and the interlayer insulator film, and this crystallization reaches to the top surface and the side surface before the silicon atoms in the top surface and the side surface are sufficiently migrated. If crystallization reaches to the top surface and the side surface, migration of silicon atoms can no longer occur, and therefore, the concaves and convexes can no longer be formed on the top surface and the side surface. As a result, it is not possible to form the concaves and convexes over the whole surface of the capacitor lower plate, and it is also not possible to avoid generation of defective regions of about 10% to 20%